Technical Field
The present application relates to generating cascode voltages for biasing and in particular, but not exclusively to, circuits and methods for such voltage generation.
Description of the Related Art
Production cost is an important consideration in the design and fabrication of any integrated circuit, such as a system on chip (SoC), as well as packages having multiple chips, such as a system-in-package. One way to reduce production cost is by reducing the number of masks used, which can be achieved by minimizing the types of devices in the design. But for some chips such as Non-Volatile Memories, which are operated utilizing relatively high voltages (e.g., used for program and Erase operations), using one type of transistor is very difficult. If a transistor is not biased properly in given Safe Operating Area (SOA) limits, then reliability issues may result in the design. As such, operation of such devices within SOA limits may be facilitated using a cascode scheme, which uses intermediate voltages for cascoding.
When a single type of transistor is used in a design, then a cascode technique may be employed to protect the transistor from stress across oxide and different junctions. Cascoding is a conventional technique to bias the gate, drain/source and bulk terminals of transistors so that they can operate within a Safe Operating Area. For example, if THH is a maximum operating voltage (normally generated from on-chip charge-pump circuitry) and ⅓ THH is the SOA limit of the transistors, then voltages of ⅔ THH and ⅓THH are needed to make a two stage cascoding scheme.
As shown in FIG. 1, a cascoding circuit 100 may utilize two PMOS transistors 101, 102 as cascode stages, with their terminals biased with ⅔THH and ⅓THH, respectively, such that no junction of the transistors 101, 102 will be stressed more than ⅓THH and SOA limits will not be exceeded.
Similarly as shown in FIG. 2, a cascoding circuit 200 may include three NMOS transistors 201, 202, 203 arranged in cascode fashion and biased in such a way that no junctions of any transistor 201, 202, 203 will be stressed more than ⅓THH. Normally, these high voltages (e.g., ⅓THH and ⅔THH) are required only during specific high voltage operations (for example, program and erase operations in Non-Volatile Memory). During non-high voltage operations, these cascoding voltages should be at a normal positive supply voltage level (e.g., VDD) or at a reference or ground (GND) level.
In order to bias the devices within a given SOA limit, intermediate voltages should be generated in such a way that they are some division of charge-pump voltage (THH) during high voltage operations, and during low voltage operations (e.g., a READ operation), the intermediate voltages should be at a normal VDD or GND level. As shown in FIGS. 1 and 2, four different voltages may be used for cascoding, and bias different terminals of the PMOS and NMOS transistors: ⅔THH_H, ⅔THH_L, ⅓THH_H and ⅓THHH_L. During high voltage operations, these voltages should be as follows: ⅔THH_H=⅔THH_L=⅔THH; and ⅓THH_H=⅓THH_L=⅓THH. In low voltage operations (e.g., when charge-pump is OFF) the voltages should be as follows: ⅔THH_H=⅓THH_H=VDD; and ⅔THH_L=⅓THH_L=GND. This is required because ⅔THH_H and ⅓THH_H signals are used to bias bulk of PMOS (i.e. NWELL) and during low voltage operation the NWELL should be biased at VDD (i.e., highest available voltage). Similarly the ⅔THH_L and ⅓THH_L signals are used to bias PWELL, which in low voltage operation should be biased at GND (i.e., lowest potential).
FIG. 3 shows a circuit 300 for implementing a conventional OPAMP-based cascode voltage generation technique. The circuit 300 includes a charge-pump 310, resistive ladder 350 (made up of resistors R1, R2, R3 and R4), comparator 320, two OPAMPS 331, 332 configured as unity gain buffers, and pull-up and pull-down logic 341, 342. If THH is the final output of the charge-pump 310, V1 and V2 are tapped from resistive ladder 350 in such a way that V1=⅔THH and V2=⅓THH. These two voltages V1 and V2 can be buffered using the two OPAMPs 331, 332. Supply voltage for the OPAMPs 331, 332 is THH. The pull-up and pull-down logic 341, 342 is utilized so that the final signals ⅔THH_H, ⅔THH_L, ⅓THH_H and ⅓THH_L can be biased at VDD and GND levels during non-HV operations.
FIG. 4 illustrates a circuit 400 for generating cascode voltages another way. Here, signals V1, V2 and V3 are taken from a resistive ladder used in a charge-pump. Signal V1 is used to bias the gates of transistors MP1, MN1 and MN6. V1 is taken in such a way that its voltage level is ⅔THH+Vtn. Signal V2 is used to bias the gates of transistors MP2, MN2 and MN7. V2 is taken in such a way that its voltage level during high voltage operation is ⅓THH+Vtn. Signal V3 is used to bias the gate of NMOS MN3. Signal V3 is taken in such a way that NMOS M3 is OFF during high voltage operations and during low voltage operation it is at VDD so that ⅔THH_L and ⅓THH_L can be shorted and taken to GND level. The circuit 400 includes a left branch 410 (including MP1, MN1, MP2, MN2, MN3, MN4 and MN5) and a right branch 420 (including MN6, MP3, MN7, MP4, MP5 and MP6). The left branch 410 is used to generate ⅔THH_L and ⅓THH_L voltages and the right branch 420 is used to generate ⅔THH_H and ⅓THH_H voltages. A constant current is used to bias the two branches 410, 420 during high voltage operation and during low voltage operation GND path is activated through NMOS switch MN5.
In the right branch 420, during low voltage operation ⅔THH_H and ⅓THH_H are forced to VDD level via MP3, MP4 and MP5 switches. During high voltage operation constant current is used to bias the branch.
The conventional cascode voltage generation circuits, such as those illustrated in FIGS. 3 and 4, suffer a variety of issues. In the OPAMP based cascode voltage generation circuit 300 of FIG. 3, some of these issues include:                1) Two OPAMPs are used as an analog buffer. OPAMPs will consume more current which is to be provided by the charge-pump. Thus, more power will be consumed, and in order to provide this current more area will be used in the charge-pump.        2) OPAMPs are working at high voltage THH (generated from charge-pump), so conventional OPAMPs cannot be used. Thus, there should be some cascoded structure inside the OPAMPs to protect the transistors.        3) In order to force the ⅔THH_H=⅓THH_H=VDD and ⅔THH_L=⅓THH_L=GND complex pull-up and pull-down logic is employed in prior art designs, which uses extra area and consumers more power.        
Some of the problems faced in the OPAMP based voltage generation circuit 300 of FIG. 3 may be overcome in the source follower based voltage generator circuit 400 shown in FIG. 4. However, that circuit also has certain problems, including the following:                1) Due to the different capacitive loads on each branch, during the ramp-up of charge-pump the ⅔THH_H signal has a different ramp rate than the ⅔THH_L signal, and similarly the ⅓THH_H signal has a different ramp rate than the ⅓THH_L signal. As these signals are used to bias the different terminals of transistors, there can be forward biasing of Bulk to Drain or Bulk to source junctions. Due to Bulk junction forward biasing, there can be a risk of latch-up in the chip.        2) Further, current is consumed by each of the two branches which are supported by the charge-pump, which results in more area and higher power consumption.        